All Superinterfaces:
CPUInfo
All Known Implementing Classes:
IntelInfoImpl
public interface IntelCPUInfo extends CPUInfo
An interface for classes that provide lowlevel information about Intel CPU's

  • Method Summary

    All Methods
    Modifier and Type
    Method
    Description
    boolean
    IsAtomCompatible()
    Returns whether the CPU implements at least an Atom level instruction/feature set.
    boolean
    IsBroadwellCompatible()
    Returns whether the CPU implements at least a Broadwell level instruction/feature set.
    boolean
    IsCore2Compatible()
    Returns whether the CPU implements at least a Core2 level instruction/feature set.
    boolean
    IsCoreiCompatible()
    Returns whether the CPU implements at least a Corei level instruction/feature set.
    boolean
    IsHaswellCompatible()
    Returns whether the CPU implements at least a Haswell level instruction/feature set.
    boolean
    IsIvyCompatible()
    Returns whether the CPU implements at least a IvyBridge level instruction/feature set.
    boolean
    IsPentium2Compatible()
    Returns whether the CPU implements at least the p6 instruction set (Pentium II or better).
    boolean
    IsPentium3Compatible()
    Returns whether the CPU implements at least a Pentium III level of the p6 instruction/feature set.
    boolean
    IsPentium4Compatible()
    Returns whether the CPU implements at least a Pentium IV level instruction/feature set.
    boolean
    IsPentiumCompatible()
    Returns whether the CPU is at least a Pentium CPU.
    boolean
    IsPentiumMCompatible()
    Returns whether the CPU implements at least a Pentium M level instruction/feature set.
    boolean
    IsPentiumMMXCompatible()
    Returns whether the CPU is at least a Pentium which implements the MMX instruction/feature set.
    boolean
    IsSandyCompatible()
    Returns whether the CPU implements at least a SandyBridge level instruction/feature set.
    boolean
    IsSkylakeCompatible()
    Returns whether the CPU implements at least a Skylake level instruction/feature set.

    Methods inherited from interface CPUInfo

    getCPUModelString, getVendor, hasABM, hasADX, hasAES, hasAVX, hasAVX2, hasAVX512, hasBMI1, hasBMI2, hasFMA3, hasMMX, hasMOVBE, hasSSE, hasSSE2, hasSSE3, hasSSE41, hasSSE42, hasSSE4A, hasTBM, hasX64
    Modifier and Type
    Method
    Description
    String
    getCPUModelString()
    Gets the CPU model description.
    String
    getVendor()
    Gets the CPU vendor.
    boolean
    hasABM()
    Also known as LZCNT
    boolean
    hasADX()
    Intel Multi-Precision Add-Carry Instruction Extensions Available in Broadwell.
    boolean
    hasAES()
    Checks if CPU supports the AES-NI instruction set.
    boolean
    hasAVX()
    Checks if CPU supports the AVX instruction set.
    boolean
    hasAVX2()
    Checks if CPU supports the AVX2 instruction set.
    boolean
    hasAVX512()
    Does the CPU supports the AVX-512 Foundation instruction set? Quote wikipedia: AVX-512 consists of multiple extensions not all meant to be supported by all processors implementing them.
    boolean
    hasBMI1()
    Checks if CPU supports the BMI1 instruction set.
    boolean
    hasBMI2()
    Checks if CPU supports the BMI2 instruction set.
    boolean
    hasFMA3()
    Checks if CPU supports the FMA3 instruction set.
    boolean
    hasMMX()
    Checks if CPU supports the MMX instruction set.
    boolean
    hasMOVBE()
    Checks if CPU supports the MOVBE instruction set.
    boolean
    hasSSE()
    Checks if CPU supports the SSE instruction set.
    boolean
    hasSSE2()
    Checks if CPU supports the SSE2 instruction set.
    boolean
    hasSSE3()
    Checks if CPU supports the SSE3 instruction set.
    boolean
    hasSSE41()
    Checks if CPU supports the SSE4.1 instruction set.
    boolean
    hasSSE42()
    Checks if CPU supports the SSE4.2 instruction set.
    boolean
    hasSSE4A()
    AMD K10 only.
    boolean
    hasTBM()
    Trailing Bit Manipulation (AMD feature)
    boolean
    hasX64()
    Checks if CPU supports the 64-bit support.

  • Method Details

    • IsPentiumCompatible

      boolean IsPentiumCompatible()
      Returns whether the CPU is at least a Pentium CPU.
      Returns:
      true if the CPU is at least a Pentium CPU

    • IsPentiumMMXCompatible

      boolean IsPentiumMMXCompatible()
      Returns whether the CPU is at least a Pentium which implements the MMX instruction/feature set.
      Returns:
      true if the CPU is at least a Pentium MMX compatible CPU

    • IsPentium2Compatible

      boolean IsPentium2Compatible()
      Returns whether the CPU implements at least the p6 instruction set (Pentium II or better). Please note that an PentimPro CPU causes/should cause this method to return false (due to that CPU using a very early implementation of the p6 instruction set. No MMX etc.)
      Returns:
      true if the CPU implements at least the p6 instruction set

    • IsPentium3Compatible

      boolean IsPentium3Compatible()
      Returns whether the CPU implements at least a Pentium III level of the p6 instruction/feature set.
      Returns:
      true if the CPU implements at least a Pentium III level

    • IsPentium4Compatible

      boolean IsPentium4Compatible()
      Returns whether the CPU implements at least a Pentium IV level instruction/feature set. Supports the SSE 2 instructions. Does not necessarily support SSE 3.
      Returns:
      true if the CPU implements at least a Pentium IV level

    • IsPentiumMCompatible

      boolean IsPentiumMCompatible()
      Returns whether the CPU implements at least a Pentium M level instruction/feature set.
      Returns:
      true if the CPU implements at least a Pentium M level

    • IsAtomCompatible

      boolean IsAtomCompatible()
      Returns whether the CPU implements at least an Atom level instruction/feature set. Supports the SSE 2 and SSE 3 instructions.
      Returns:
      true if the CPU implements at least an Atom level instruction/feature set

    • IsCore2Compatible

      boolean IsCore2Compatible()
      Returns whether the CPU implements at least a Core2 level instruction/feature set. Supports the SSE 3 instructions.
      Returns:
      true if the CPU implements at least a Core2 level instruction/feature set

    • IsCoreiCompatible

      boolean IsCoreiCompatible()
      Returns whether the CPU implements at least a Corei level instruction/feature set. Supports the SSE 3, 4.1, 4.2 instructions. In general, this requires 45nm or smaller process. This is the Nehalem architecture.
      Returns:
      true if the CPU implements at least a Corei level instruction/feature set

    • IsSandyCompatible

      boolean IsSandyCompatible()
      Returns whether the CPU implements at least a SandyBridge level instruction/feature set. Supports the SSE 3, 4.1, 4.2 instructions. Supports the AVX 1 instructions. In general, this requires 32nm or smaller process.
      Returns:
      true if the CPU implements at least a SandyBridge level instruction/feature set

    • IsIvyCompatible

      boolean IsIvyCompatible()
      Returns whether the CPU implements at least a IvyBridge level instruction/feature set. Supports the SSE 3, 4.1, 4.2 instructions. Supports the AVX 1 instructions. In general, this requires 22nm or smaller process. UNUSED, there is no specific GMP build for Ivy Bridge, and this is never called from NativeBigInteger. Ivy Bridge is a successor to Sandy Bridge, so use IsSandyCompatible().
      Returns:
      true if the CPU implements at least an IvyBridge level instruction/feature set

    • IsHaswellCompatible

      boolean IsHaswellCompatible()
      Returns whether the CPU implements at least a Haswell level instruction/feature set. Supports the SSE 3, 4.1, 4.2 instructions. Supports the AVX 1, 2 instructions. Supports the BMI 1, 2 instructions. WARNING - GMP 6 uses the BMI2 MULX instruction for the "coreihwl" binaries. Only Core i3/i5/i7 Haswell processors support BMI2. Requires support for all 6 of these Corei features: FMA3 MOVBE ABM AVX2 BMI1 BMI2 Pentium/Celeron Haswell processors do NOT support BMI2 and are NOT compatible. Those processors will be Sandy-compatible if they have AVX 1 support, and Corei-compatible if they do not. In general, this requires 22nm or smaller process.
      Returns:
      true if the CPU implements at least a Haswell level instruction/feature set

    • IsBroadwellCompatible

      boolean IsBroadwellCompatible()
      Returns whether the CPU implements at least a Broadwell level instruction/feature set. Supports the SSE 3, 4.1, 4.2 instructions. Supports the AVX 1, 2 instructions. In general, this requires 14nm or smaller process. NOT FULLY USED as of GMP 6.0. All GMP coreibwl binaries are duplicates of binaries for older technologies, so we do not distribute any. However, this is called from NativeBigInteger. Broadwell is supported in GMP 6.1 and requires the ADX instructions. Requires support for all 7 of these Corei features: FMA3 MOVBE ABM AVX2 BMI1 BMI2 ADX Pentium/Celeron Broadwell processors that do not support these instruction sets are not compatible. Those processors will be Sandy-compatible if they have AVX 1 support, and Corei-compatible if they do not.
      Returns:
      true if the CPU implements at least a Broadwell level instruction/feature set

    • IsSkylakeCompatible

      boolean IsSkylakeCompatible()
      Returns whether the CPU implements at least a Skylake level instruction/feature set. Supports the AVX-512 instructions.
      Returns:
      true if the CPU implements at least a Skylake level instruction/feature set