See: Description
| Interface | Description |
|---|---|
| AMDCPUInfo | An interface for classes that provide lowlevel information about AMD CPU's |
| CPUInfo | An interface for classes that provide lowlevel information about CPU's |
| IntelCPUInfo | An interface for classes that provide lowlevel information about Intel CPU's |
| VIACPUInfo | Moved out of CPUID.java |
| Class | Description |
|---|---|
| AMDInfoImpl | Moved out of CPUID.java
Ref: https://en.wikipedia.org/wiki/List_of_AMD_CPU_microarchitectures
Ref: https://gmplib.org/repo/gmp/file/tip/config.guess |
| CPUID | Retrieves CPU details via the x86 CPUID instruction through a native JNI library (jcpuid). |
| CPUID.CPUIDResult | Holds the four 32-bit register values (EAX, EBX, ECX, EDX) returned
by a single CPUID instruction call. |
| CPUIDCPUInfo | Moved out of CPUID.java
Ref: http://en.wikipedia.org/wiki/CPUID |
| IntelInfoImpl | Identifies Intel CPUs via CPUID and exposes instruction set support flags. |
| VIAInfoImpl | Moved out of CPUID.java |
| Exception | Description |
|---|---|
| UnknownCPUException | UnknownCPUException Extends RuntimeException. |
CPU identification and instruction set detection via the CPUID instruction. Originally from Freenet, heavily modified for I2P+.
CPUInfo (interface)
├── IntelCPUInfo (interface)
│ └── IntelInfoImpl (implementation)
├── AMDCPUInfo (interface)
│ └── AMDInfoImpl (implementation)
└── VIACPUInfo (interface)
└── VIAInfoImpl (implementation)
CPUIDCPUInfo — base class implementing CPUInfo feature-flag methods
CPUID — static JNI bridge to native CPUID calls + brand string helpers
UnknownCPUException — thrown when the CPU cannot be identified
Each vendor-specific implementation (IntelInfoImpl, AMDInfoImpl, VIAInfoImpl) uses a two-tier identification approach:
The brand string, when present, overrides the model-based name for display purposes. The model-based switch always runs to set the internal instruction set compatibility flags (IsSandyCompatible, IsHaswellCompatible, IsZen4Compatible, etc.).
The compatibility flags (e.g. IsHaswellCompatible,
IsZen4Compatible) are checked by callers to select optimized code paths.
The primary consumer is NativeBigInteger, which loads vendor-specific
GMP native binaries (coreiwl, coreibwl, etc.) based on these flags.
Detected instruction sets include: MMX, SSE/2/3/4.1/4.2/4a, AVX/AVX2/AVX-512, AES-NI, BMI1/2, FMA3, ADX, TBM, MOVBE, ABM (LZCNT), and x86-64.
| Vendor | Family Range | Implementation |
|---|---|---|
| Intel | Family 4, 6, 7, 15 | IntelInfoImpl |
| AMD | Family 5–26 | AMDInfoImpl |
| VIA/Centaur | Family 6 (C3/Nano) | VIAInfoImpl |
NativeBigInteger — selects GMP native binary (coreihwl, coreibwl, coreisbr, zen, zen2, etc.)CryptixAESEngine — uses CPUID for AES-NI detectionRouter — logs CPU info at startupWarning: Not recommended for external use, not maintained as a public API. The implementation may change between I2P versions without notice.