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Package freenet.support.CPUInformation

CPU identification and instruction set detection via the CPUID instruction.

See: Description

Package freenet.support.CPUInformation Description

CPU identification and instruction set detection via the CPUID instruction. Originally from Freenet, heavily modified for I2P+.

Architecture

    CPUInfo (interface)
        ├── IntelCPUInfo (interface)
        │       └── IntelInfoImpl (implementation)
        ├── AMDCPUInfo (interface)
        │       └── AMDInfoImpl (implementation)
        └── VIACPUInfo (interface)
                └── VIAInfoImpl (implementation)

    CPUIDCPUInfo — base class implementing CPUInfo feature-flag methods
    CPUID — static JNI bridge to native CPUID calls + brand string helpers
    UnknownCPUException — thrown when the CPU cannot be identified

Identification Strategy

Each vendor-specific implementation (IntelInfoImpl, AMDInfoImpl, VIAInfoImpl) uses a two-tier identification approach:

  1. Brand string (CPUID leaves 0x80000002–0x80000004): Returns the exact marketing name (e.g. "AMD Ryzen 9 9900X 12-Core Processor" or "Intel Core i9-14900K"). Always accurate when available on modern CPUs.
  2. Model number fallback: For very old CPUs without brand string support, the processor is identified from CPUID family/model/extended-model/extended-family values and matched against a table of known microarchitectures.

The brand string, when present, overrides the model-based name for display purposes. The model-based switch always runs to set the internal instruction set compatibility flags (IsSandyCompatible, IsHaswellCompatible, IsZen4Compatible, etc.).

Instruction Set Flags

The compatibility flags (e.g. IsHaswellCompatible, IsZen4Compatible) are checked by callers to select optimized code paths. The primary consumer is NativeBigInteger, which loads vendor-specific GMP native binaries (coreiwl, coreibwl, etc.) based on these flags.

Detected instruction sets include: MMX, SSE/2/3/4.1/4.2/4a, AVX/AVX2/AVX-512, AES-NI, BMI1/2, FMA3, ADX, TBM, MOVBE, ABM (LZCNT), and x86-64.

Supported Vendors

Supported CPU vendors and implementations
VendorFamily RangeImplementation
IntelFamily 4, 6, 7, 15IntelInfoImpl
AMDFamily 5–26AMDInfoImpl
VIA/CentaurFamily 6 (C3/Nano)VIAInfoImpl

Callers Within I2P

Warning: Not recommended for external use, not maintained as a public API. The implementation may change between I2P versions without notice.

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